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Rejuvenation of Diverse FPGA Softcores in a SoC

Project

Project Details

Program
Computer Science
Field of Study
FPGA, System on Chip, Replication
Division
Computer, Electrical and Mathematical Sciences and Engineering
Faculty Lab Link
https://www.kaust.edu.sa/en/study/faculty/paulo-verissimo
Center Affiliation
Resilient Computing and Cybersecurity Center

Project Description

A field-programmable gate array (FPGA) is an integrated circuit designed to be reconfigured by the user after manufacturing to build a System-on-Chip (SoC) embedded device. The needed logic is usually implemented as a software image and then instantiated on the FPGA to inherit the nice properties of hardware, like higher speed and better security. Unfortunately, since the image itself, e.g., a Softcore that represents a Processing Unit, is a software, it is prone to faults and vulnerabilities that manifest after instantiation on the FPGA. Unfortunately, an Advanced Persistent Threat (APT) is possible if a determined adversary managed to discover a new vulnerability to initiate a zero-day, leaving no chance for classical detection and prevention tools to recover. In addition, the softcore can include bugs and glitches that manifest only at run time. Fault and Intrusion Tolerance (FIT) is a technique used to make a process resilient to such attacks by masking them. A FIT protocol replicates the processors, i.e., a softcore in our case, by running three versions simultaneously, and collecting a majority agreement (or consensus) on each operation. If the majority (e.g., 2/3 processors) did not fail at the same instant, the fault is masked, and the SoC continues operation as designed. This requires some level of diversity in the running softcore to increase the chances of independence of failures.

About the Researcher

Paulo Esteves-Verissimo
Professor, Computer Science
Computer, Electrical and Mathematical Science and Engineering Division

Affiliations

Education Profile

  • Ph.D., Electrical and Computer Engineering, University of Lisbon (PT), 1990
  • MSc, Electrical and Computer Engineering, University of Lisbon IST (PT), 1984
  • Lic., Electrical Engineering, University of Lisbon IST (PT), 1978

Research Interests

Professor Esteves-VerA­ssimo is currently interested in architectures, middleware and algorithms for resilient modular and distributed computing. It is increasingly believed that Resilient Computing will become the main paradigm for achieving secure and dependable operation of computer systems and networks in a near future, improving classic Cybersecurity techniques. This is due to important intrinsic characteristics of this B.o.K., such as: common approach to accidental and malicious faults/attacks; incremental and adaptive protection against polymorphic threat surfaces; elasticity, plasticity and sustainability. To this end, he investigates such paradigms and techniques reconciling security and dependability, as well as novel ways to apply them in order to achieve system resilience, in areas like: autonomous vehicles from earth to space; distributed control systems; digital health and genomics; SDN-based infrastructures; or blockchain and cryptocurrencies. His research is published in over 200 peer-refereed international publications and 5 international books. He was invited as well to present it in more than 70 keynote speeches or distinguished lectures at reputed venues. Esteves-VerA­ssimo also has a solid systems and engineering track record, having contributed to the design and engineering of several advanced industrial prototypes of distributed, fault-tolerant, secure or real-time systems, emerging from R&D projects he took part in.

Selected Publications

  • Jiangshan Yu, David Kozhaya, JA©rA©mie Decouchant, Paulo Esteves-VerA­ssimo. RepuCoin: Your Reputation is Your Power (2019). In IEEE Trans. on Computers, 68(8), 1225-1237.
  • Kreutz, Diego; Ramos, F. M. V.; Verissimo, Paulo; Rothenberg, C. E.; Azodolmolky, S.; Uhlig, S. ""Software-Defined Networking: A Comprehensive Survey"", in Proceedings of the IEEE (2015), 103(1), 14-76.
  • Giuliana Veronese, Miguel Correia, Alysson Bessani, Lau Lung, Paulo Verissimo, ""Efficient Byzantine Fault-Tolerance"", IEEE Tacs. on Computers, vol. 62, no. 1, Jan. 2013.
  • Paulo Sousa, Alysson Bessani, Miguel Correia, Nuno Ferreira Neves, Paulo VerA­ssimo. Highly Available Intrusion-Tolerant Services with Proactive-Reactive Recovery. IEEE Tacs. on Parallel and Distributed Systems. Apr. 2010.
  • VerA­ssimo, P., Casimiro, A.: The timely computing base model and architecture. IEEE Tacs. on Computers, Special Issue on Asynchronous Real-Time Distr. Systems (2002).
  • D. Powell, D. Seaton, G. Bonn, P. VerA­ssimo, and F. Waeselynk. The Delta-4 approach to dependability in open distributed computing systems. In N. Suri, C. Walter, and M. Hugue, editors, Adv. in Ultra-Dependable Distr. Sys. IEEE Computer Society, 1995.

Desired Project Deliverables

The goal of this project is to experiment running an FIT we are implementing on a diverse softcores, e.g., Microblaze, RISC-V, Openpiton, etc., on an FPGA and simulate some fault or attacks. We are experimenting the concept on a Xilinx Zinc board using equivalent replicas. The objectives are to check the feasibility of running the FIT with different softcore types and evaluate the behavior in action. The intern will acquire all this knowledge and publish the results by working with a team of experts.

Recommended Student Background

field-programmable gate array
System on Chip
Replication
Verilog, VHDL
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